### Summary

Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other’s ideas stronger. That happens because each of us believes we can create something wonderful and share it with the world, changing lives for the better. It’s the diversity of our people and their thinking that inspires the innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you’ll do more than join something — you’ll add something. Do you have a passion for innovation and technical excellence? Do you thrive on solving complex problems that push the boundaries of what's possible? Join our team to verify innovative, high-throughput cellular baseband modems and transceiver link controllers that power communication for millions of users worldwide.

### Description

As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems. Working on innovative baseband modems and RF link controllers for Apple's SOCs, you'll craft highly reusable UVM verification environments that set the standard for quality and efficiency. You'll develop comprehensive coverage-driven and directed test cases that thoroughly validate complex IP and subsystem designs, working closely with multi-functional teams throughout the process. In this role, you'll drive methodology innovation by deploying sophisticated tools and techniques that elevate verification practices and ensure tape-out readiness. Collaborating with product development teams across Apple, you'll help deliver cellular systems that redefine industry capabilities and enhance customer experiences globally. This position offers exceptional opportunities to deepen your expertise across cellular protocols, complex IP and subsystem architectures, advanced fabric protocols, and sophisticated debug methodologies. You'll gain experience with best-in-class design verification practices, co-verification techniques with models and firmware, and industry-standard low-power architectures. We're looking for engineers with hands-on ASIC design verification experience using reusable verification methodologies such as UVM. The ideal candidate excels at detailed test planning, adapts optimally to evolving requirements, has knowledge of the latest ML-based tools to improve productivity, and is driven to achieve the highest quality standards. You thrive in collaborative environments and are eager to address the verification challenges inherent in complex, high-performance cellular systems. If you want to contribute to products that impact customers worldwide while advancing your technical expertise, we'd love to hear from you.

### Responsibilities

- Construct detailed test plans for the various components of the design, including use cases, in collaboration with multi-functional teams.
- Create coverage-driven verification plans from specifications, review, and refine to achieve coverage targets.
- Architect UVM-based, reusable test benches with components for stimulus, checkers, VIPs, and reference models.
- Leverage Large Language Models (LLMs) to enhance verification processes, improving efficiency and quality.
- Design and implement ML-driven workflows that increase team productivity and overall quality of verification.
- Implement test plans from RTL simulation bring-up to sign-off, report, and debug failures.
- Maintain regressions and report the verification progress against test plans and coverage metrics.

### Minimum Qualifications

- Multiple years of relevant industry experience, including several years of experience in a leadership position.
- Strong knowledge of System Verilog and UVM.
- Highly skilled in System C, C/C++, and/or Python/Perl.
- Highly proficient in developing and establishing DV Methodologies.
- Good experience in using LLMs and MCPs.
- Good experience with developing Python-based automation solutions.
- Experience with constraint random testing, SVA, and coverage-driven verification.
- Strong test planning and problem-solving skills, and advanced communication and interpersonal skills.

### Preferred Qualifications

- You hold a PhD or Master of Science degree in Electrical Engineering/Computer Science or equivalent, or a BSc. Degree plus seasoned industry and leadership experience.
- Experience in C/C++ modeling for design verification would be desirable.
- Knowledge of 4G/5G cellular physical layer operation (3GPP) would be a bonus.
- Experience with the verification of embedded processor cores.
- Hands-on verification experience of Bus Fabric, NOC, AHB, AXI, based bus architecture in the UVM environment would be desirable.
- Experience using LLMs to improve efficiency and quality of verification.
- Understanding of prompt engineering and LLM workflow optimization.
- Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities.